As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. Particularly, verifying at-speed performance of integrated circuits is important to ensure a satisfactory shipped part quality level (SPQL). In the past, at-speed performance of integrated circuits was typically verified using functional tests. However, as the complexity and density of circuits continue to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. For example, it is not feasible to develop functional tests for today's multi-million gate designs to achieve satisfactory defect coverage due to the prohibitive cost of such development. Conventionally, the scan-based delay testing approach is used as a low-cost alternative to functional testing for verifying at-speed performance of integrated circuits.
Timing failures caused by delays may result in circuitry logic failure and eventually lead to a system failure. Thus, in the scan-based delay testing approach, performance failures are modeled as delay-causing faults and test patterns are generated by an automatic test pattern generator (ATPG).
Transition delay fault and path delay fault models are known to provide a good coverage of delay-causing faults. The transition delay fault model targets every node in the design for a slow-to-rise and a slow-to-fall delay fault whereas the path delay fault model targets the cumulative delay through paths in the circuit. Typically, the transition delay fault (TDF) test model requires two-pattern tests, involving a first pattern and a second pattern. The TDF model is commonly used in the industry since it is simple and existing ATPG algorithms can be easily adapted to generate tests for TDF faults. Conventionally, there are two accepted approaches of testing for TDF faults, such as skewed-load testing and broadside testing. Both of the two approaches may generate the first pattern called an initialization pattern in a similar fashion. However, the two approaches differ in how the second pattern called the launch pattern is obtained.
In the broadside testing, the launch pattern is derived from the circuit response to the initialization pattern. The broadside testing requires two cycles of sequential processing. The sequential processing of the broadside testing results in less than optimal fault coverage using commercially available ATPG tools and, thus, results in long run time and low coverage.
In the skewed-load testing, the launch pattern is obtained by a one-bit shift of the initialization pattern. The test response to the second pattern is captured by applying a system clock pulse. Generally, the skewed-load testing achieves higher fault coverage than the broadside testing. However, the skewed-load testing requires that scan enable (SEN) signal has to change fast and accommodate the system clock period. Presently, the design effort involved in designing a fast SEN signal and the resulting impact on turnaround time is considered unacceptable for many designs. Consequently, the broadside testing is often preferred over the skewed-load testing in scan designs that use the system clock for scan operations since broadside testing does not requires a fast (at-speed) scan enable signal. As such, some restrictions on scan designs may force testers to employ the broadside testing even though it does not provide optimal transition delay test (TDF) fault coverage.
Therefore, it would be desirable to provide a method and system which can overcome the drawback of the broadside testing and achieve greater TDF coverage with a minimal test costs and chip area overhead.